vhdl - variable must be constrained error -

i getting error , don't understand why.

my code :

 library ieee; use ieee.std_logic_1164.all; use work.func_pack.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --use ieee.numeric_std.all; entity letters_arranger   port ( clock, reset,start,rdy_to_get_new_letter  :in   std_logic; -- asuuming clock 27 m hz  select_input : in integer;         reg : out std_logic_vector(7 downto 0);   drive_letter : out std_logic  );  end letters_arranger ; architecture behave of letters_arranger     type state (idle, set_str, send_str,endstring);      signal cur_state: state;     --signal str :string :="                                              "&cr;     signal str :string :="                                              "&cr;        signal counter :integer;      constant letters_max : integer := 47;  begin   pro:process(clock,reset) variable data_count : integer range 0 10 :=0; begin if (reset='1')                  cur_state <= idle;    elsif  rising_edge(clock)  case cur_state      when idle=>           drive_letter<='0';          if start = '1'          cur_state <= set_str;          counter<=0;          elsif counter = letters_max             cur_state <= endstring;           elsif rdy_to_get_new_letter ='1'          cur_state <= send_str;         end if;      when set_str =>              str <= select_str(select_input);         counter<=1;-- check char pos indx start fr 0 or 1      when send_str =>         cur_state <= idle;         if counter<=str'length             counter<=counter+1;         end if;              reg<=conv_std_logic_vector(character'pos(str(counter)),8);               drive_letter<='1';      when    endstring =>          --need          cur_state <= idle;       when others => null; end case;  end if;   end process;  end behave; 

and funcpack (only function select_str relevant believe ):

------------------------ func_pack.vhd program ------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package func_pack  ------------type decalration --------------- subtype byte std_logic_vector(7 downto 0); type special_message array(0 4,0 100) of byte;  --------------------------------------------  function parity_calc ( data : std_logic_vector(7 downto 0) )return std_logic ; function to_7seg ( data:integer range 0 9)return std_logic_vector;       function select_str ( indx:integer range 0 9) return string; end func_pack; ---------------------------------------------------------------------------------------------------------------------------- package body func_pack  --parity_calc--     function parity_calc ( data : std_logic_vector(7 downto 0) )return std_logic variable temp : std_logic ; begin     temp := data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7);     return (temp); end parity_calc;  -----------------------------------------------------------------------------    ------------       ------------------ 7eg  convert function ---------------------------------------------  function to_7seg ( data:integer range 0 9)return std_logic_vector variable temp:std_logic_vector (6 downto 0):=(others=>'1'); begin case     data      when  0 => temp :="1000000";    -- 40h     when  1 => temp :="1111001";    -- 79h     when  2 => temp :="0100100";    -- 24h     when  3 => temp :="0110000";    -- 30h     when  4 => temp :="0011001";    -- 19h     when  5 => temp :="0010010";    -- 12h     when  6 => temp :="0000010";    -- 02h     when  7 => temp :="1111000";    -- 78h     when  8 => temp :="0000000";    -- 00h     when  9 => temp :="0010000";    -- 10h     when others => null; end case; return (temp); end to_7seg;  function select_str ( indx:integer range 0 9) return string variable temp:string;  begin case     indx      when  0 => temp :="                                              "&cr;       when  1 => temp :="v18                                           "&cr;       when  2 => temp :="w300                                          "&cr;       when  3 => temp :="splease choose 1 branch line out of 3 possible"&cr;       when  4 => temp :="syou chose  branch number 1                   "&cr;       when  5 => temp :="syou chose  branch number 2                   "&cr;       when  6 => temp :="syou chose  branch number 3                   "&cr;        when others => temp:="                                              "&cr;    end case; return (temp); end select_str;   -----------------------------------------------------------------------------------   --"v18" --"w300" -- --"splease choose 1 branch line out of 3 possible" -- 46 . --"syou choosed  branch number 1" --"syou choosed  branch number 2" --"syou choosed  branch number 3" --29 --"sconnecttinngg" -- 14 --"si sorry couldn't find branch , tried reach"    --59 --13 -- =d in hex == <cr> . must sent in end of each line -- --type message_preset record --  speed: array(0 2) of byte ; --  volume: array(0 3) of byte; --  cr : integer range 0 255; --end record; --signal message_set : message_preset := (,,); -------------------------------------------------------------------------    ---------  end func_pack; 

when running first code top-level entity error :

vhdl error @ letters_arranger.vhd(21) variable must constrained . line 21 line

  signal str :string :="                                              "&cr;    

in vhdl (and globally in hardware description) need constrain of signals. otherwise, synthesizer can't allocate needed resources.

that's why should write range of string :

signal str :string(1 47) :="                                              "&cr;  

(if didn't fail in counting spaces)