structural vhdl: creating a "main function" -

i create structural vhdl file implements "main" function. "top-level" file design , program runs code prog. assuming fulladd_pack contains fulladd component, how "link" 2 vhdl files?

*i don't arguments in main in order work.

-- design.vhdl library ieee; use ieee.std_logic_1164.all; use work.fulladd_pack.all;  entity design     port(cin        :   in std_logic;             x,y     :   in  std_logic_vector(15 downto 0);             s       :   out std_logic_vector(15 downto 0);             cout, on  :   out std_logic); end design;  architecture struct of design signal c,temp   :   std_logic_vector(1 15); begin             main: prog port map(cin,x,y,s,c,cin); end struct;  

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 -- prog.vhdl library ieee; use ieee.std_logic_1164.all; use work.fulladd_pack.all;  entity prog     port(cin        :   in std_logic;             x,y     :   in  std_logic_vector(15 downto 0);             s       :   out std_logic_vector(15 downto 0);             cout, on  :   out std_logic); end prog;  architecture struct of prog signal c,temp   :   std_logic_vector(1 15); begin             instance0: fulladd port map(cin,x,y,s,c,cin);             output: fulladd port map(cin,x,y,s,c,cin);   end struct;  

you've missed point. vhdl, "programming language", models concurrency, dataflow, , passage of time. model composed of large numbers of elements ('processes') data ('signals') flowing between them. built-in kernel in simulator handles concurrency , time flow.

at "top level", write testbench, instantiates model, , apply stimulus (by driving signals inputs model). stimulus forces data around model. carries on until stop providing stimulus, @ point everthing else (should) stop.

so, no main. write testbench. 'linking' internal concept in simulator; forget it. simulate source files together.