Verilog error while declaring a array -

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reg [11:0] rom_sin_type [0:4095]= '{12'h000, 12'h003, 12'h006, 12'h009, 12'h00d, 12'h010, 12'h013, 12'h016, .....};

in verilog,when synthesizing above line of code contains 4096 values, each of 12 bit, showing error below given.

expecting ';', found '='

expecting 'endmodule', found '{'

please can me , how overcome problem?

verilog not support '{} syntax. systemverilog (ieee std 1800-2012) feature; refer § 5.10 structure literals, § 5.11 array literals, § 7.2.2 assigning structures, § , 10.9 assignment patterns.

you can either enable systemverilog (all modern verilog simulators systemverilog simulators) or assign the verilog way:

reg [11:0] rom_sin_type [0:4095]; initial begin   rom_sin_type[0] = 12'h000;   rom_sin_type[1] = 12'h003;   rom_sin_type[2] = 12'h006;   rom_sin_type[3] = 12'h009;   ..... end

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