How to load a text file on a ram in VHDL? -

i have text file describing image in terms of it's rgb components want load file on fpga produce rgb signal if kind enough enlighten me thankful

okey came there's problem synthesis taking forever finish, think problem here ??!

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use std.textio.all;   -- uncomment following library declaration if using -- arithmetic functions signed or unsigned values --use ieee.numeric_std.all;  -- uncomment following library declaration if instantiating -- xilinx primitives in code. --library unisim; --use unisim.vcomponents.all;  entity rgb_gen    port(clk : in std_logic;        en : in std_logic;          r,g,b : out std_logic);  end rgb_gen;  architecture behavioral of rgb_gen    type ram array (0 611) of bit_vector(203 downto 0);    impure function initramfromfile(filename : in string) return ram     file readfile : text in filename;    variable lineread : line;     variable my_ram : ram;      begin        in ram'range loop          readline(readfile, lineread);          read(lineread, my_ram(i));      end loop;       return my_ram;    end function;    function tostd(b : in bit) return std_logic   begin             if b = '1'             return '1';         else             return '0';       end if;   end function;    signal my_ram : ram := initramfromfile("c:\users\mos_x\desktop\output.txt");    begin      process(clk)       variable x : integer := 0;      variable y : integer := 0;       begin       if rising_edge(clk)        if en = '0'            r <= '0';             g <= '0';             b <= '0';         else             r <= tostd((my_ram(y)(x)));             g <= tostd((my_ram(y + 204)(x)));             g <= tostd((my_ram(y + 408)(x)));                end if;         if x = 203             x := 0;          if y = 203              y := 0;          else             y := y + 1;            end if;         else             x := x + 1;         end if;      end if;   end process;  end behavioral; 

so problem 2 counters in code incrementing when enable signal 0 causes static

 if rising_edge(clk)        if en = '0'            r <= '0';             g <= '0';             b <= '0';         else             r <= tostd((my_ram(y)(x)));             g <= tostd((my_ram(y + 204)(x)));             g <= tostd((my_ram(y + 408)(x)));                if x = 203                x := 0;             if y = 203                 y := 0;             else             y := y + 1;               end if;           else                   x := x + 1;           end if;        end if;       end if; 

instead of

 if rising_edge(clk)        if en = '0'            r <= '0';             g <= '0';             b <= '0';         else             r <= tostd((my_ram(y)(x)));             g <= tostd((my_ram(y + 204)(x)));             g <= tostd((my_ram(y + 408)(x)));                end if;         if x = 203             x := 0;          if y = 203              y := 0;          else             y := y + 1;            end if;         else             x := x + 1;         end if;      end if; 

would fix problem